Getting started in verilog FPGA design with Arrow's LPRP Altera board

Arrow's LPRP board has lots of stuff, but a simple getting started project would be to just blink a LED. The oscillator clock to the FPGA is 48 MHz, we'll divide it down.

blink.v:

  module blink (
    input CLK_48_MHZ,
    input USER_PB,
    output [3:0] USER_LED) ;
    wire reset_l = USER_PB ;
    reg [27:0] count1 ;
    always @ (posedge CLK_48MHZ or negedge reset_l)
      if (~reset_l)
        count1 <= 0 ;
      else
         count1 <= count1 + 1 ;
    assign USER_LED = count1[27:24] ;
  endmodule

Counter-intuitive logic minimization

I was wrestling with verilog code that wasn't meeting timing, and my attempt to help one path actually made it worse. It's an interesting example.

The code was like so:

if ((var1 - var2) > 15) then
...

I figured that if I created a shadow version of var1 that was (var1 - 15); we can call it var1_m15), I could rewrite this as:

if (var1_m15 > var2) then
...

BUT, this code actually had worse timing. It turns out that "M > 15" is semi-magical - it's simply (M[n:3] != 0). So if in the first case we have intermed = var1 - var2, and in the second case we have intermed = var1_m15 - var2, then the second case OR's all of the n+1 bits of intermed, and the first case OR's just n-3 bits of intermed. A very minor difference, but interesting/amusing?